1. Field of the Invention
This invention relates in general to computer system interconnect technologies, and more particularly, to an enhanced ATM (Asynchronous Transfer Mode) switch for use as a universal computer system interconnect.
2. Description of Related Art
SONET (Synchronous Optical Network) and ATM differ from data services like frame relay and SMDS (Switched Multimegabit Data Service) in that they serve as both address carrier infrastructure and customer services. SONET can serve as the underlying transport for ATM, which in turn can be used to support a variety of other services, such as frame relay and voice.
SONET is a transmission technology, while ATM is a switching technology. Transmission covers the way data is encoded and transported across the network and covers such aspects as the network's data rates, multiplexing schemes, encoding techniques, and transmission media. Switching involves the means used to route the data across the network.
SONET does not apply directly to switches. Rather, it specifies the interfaces between switches that are linked by optical fiber. While SONET does not apply to switches, an ATM switch or its central-office counterpart or even a LAN switch can be fitted with a SONET interface.
Currently, SONET is being deployed on public networks around the world. Thus, pairing SONET transmission technology and ATM switching technology will provide extremely fast, superstable switched public networks with the capability to handle all forms of information, i.e., data, voice, and video.
One of the key features of ATM is that it spans the local and wide area. The technology begins with voice, data, and video, and then slices and dices them into 53-byte cells. The 53-byte cells are then transmitted over highspeed circuits. Intelligent end equipment takes care of segmentation and reassembly (SAR).
ATM networks are provisioned much the same as frame relay networks. Subscribers select access and port speeds and a sustained information rate (SIR), which is comparable to frame relay's committed information rate (CIR). For example, subscriber traffic can enter a carrier's ATM network at 45 Mbit/s with a SIR of 10 Mbit/s. The traffic is guaranteed to travel through the network at 10 Mbit/s but can burst to higher bit rates when network capacity is available.
Because ATM is ideal for switch cost and the fact that it is designed to carry voice, data and video, ATM is quickly becoming the favored Local Area Network (LAN) technology. As a result, many companies are now shipping ATM switches that are ATM based and provide translations to other LAN technologies such as Ethernet, Token ring, and T1. Further, ATM networks are already replacing most other WANs, MANs and LANs. It is also a minor addition to include the regular office telephone communications function in an ATM based link to the office.
Nevertheless, present day computer systems have a multitude of interconnect technologies. These include communications interconnects such as Ethernet, Token ring, and Bi-sync. In addition, there are peripheral interconnects such as SCSI, SSA or Fibre Channel. Further, there may be special high performance system interconnects that provide low latency CPU node to CPU node messages or cache coherency traffic. One example of such an interconnect is the Scaleable Coherent Interface that supports cache coherency traffic so that multiple nodes of a symmetric multi-processing system work as if connected on the same memory bus. This multitude of interconnect technologies is expensive, difficult to manage, difficult to maintain and often fails.
At the present time, CPU node interconnect and peripheral interconnects are not currently provided for by ATM technology. For example, massively parallel, shared-nothing architectures require message passing between nodes to coordinate parallel computing operations. FIG. 11 illustrates a massively parallel processing system 1100. Processing systems 1102, 1104, 1106, 1108 are interconnected by a node interconnect cloud 1110. The node interconnect cloud 1110 may comprise a star, ring or bus topology. Accordingly, node to node messaging between the processing systems 1102, 1104, 1106, 1108 are possible. The processing systems are also connected to a LAN cloud 1112 for communicating with clients. Further, each processing system 1102, 1104, 1106, 1108 may access a plurality of disk arrays 1122, 1124, 1126, 1128 via a peripheral bus 1130 such as a SCSI bus. However, message latencies from application to application must be orders of magnitude faster than currently provided by existing LAN latencies.
Shared file system architectures require either a complete or partial implementation of a distributed file system manager providing various bookkeeping, file locking, and synchronization functions. FIG. 12 illustrates a shared file system architecture 1200. Processing systems 1202, 1204, 1206, 1208 are interconnected by a distributed file system manager interconnect cloud 1210. The distributed file system manager interconnect cloud 1210 may comprise a star, ring or bus topology. Again, node to node messaging between the processing systems 1202, 1204, 1206, 1208 are possible. The processing systems are also connected to a LAN cloud 1212 for communicating with clients. Further, each processing system 1202, 1204, 1206, 1208 may access a plurality of disk arrays 1222, 1224, 1226, 1228 via, for example, a SCSI bus 1230. The latencies required are even faster than massively parallel processing systems to support performance goals of shared file systems. Latencies for shared file systems should be in the 10 us and lower range.
FIG. 13 illustrates a symmetric multiprocessor processing system 1300. In the symmetric multiprocessor processing system 1300, a plurality of central processing units 1302, 1304, 1306, 1308 are connected to an I/O sub system 1320 and memory sub system 1330 via memory bus 1340. Thus, the symmetric multiprocessor processing system 1300 facilitates I/O operation between a CPU and the I/O sub system 1320. Each CPU may perform cache coherency messaging between a respective central processing unit. Finally each central processing unit may perform a memory operation between itself and the memory sub system 1330. Symmetric multiprocessor architecture requires cache coherency with latencies below 2 us.
Since cache coherency traffic may be high, through-put is still another issue. Accordingly, computer nodes must have special ATM interface adapters designed to minimize host CPU access to an ATM link and also to connect directly to the ATM switch core.
In addition to node interconnects, peripheral interconnect solutions are needed to interface with an ATM switch. Fibre Channel is presently becoming the new peripheral interconnect of choice, replacing parallel bus SCSI based interconnect.
Fibre Channel is a high speed (1 Gbit/Sec) serial bus interface. Fibre Channel is described in a number of documents, with the core document being entitled, The "Fibre Channel Physical and Signaling Layer" (FC-PH). Fibre Channel technology includes the description of the Fibre Channel packet format, and a suite of Fibre Channel protocols, which can be used to transport some form of payload in either a reliable or unreliable fashion. By defining the contents of the payload and any associated upper level protocols, Fibre Channel can be used to communicate amongst a variety of computing devices. One of the reasons that Fibre Channel is so popular is that one of the payloads and upper level protocols which can be mapped, is the protocol for SCSI. This allows many vendors to use most of the software that is written for peripherals while simultaneously providing them with the benefits of Fibre Channel, the most important of which are Fibre Channel's ability to provide them with a serial bus which has a much higher performance than parallel SCSI buses, and requires much smaller cabling.
The serial SCSI protocol that is supported by Fibre Channel is known through the name, "Fibre Channel Protocol for SCSI", or the aliases, "SCSI Fibre Channel Protocol", or "FCP". The document entitled, the "Fibre Channel Protocol for SCSI", describes the SCSI packet formats, for SCSI Command, Data, and Status packets, as well as the SCSI protocol, pertinent to performing SCSI operations over Fibre Channel. In a purely Fibre Channel environment, SCSI packets are transported as payloads encapsulated within Fibre Channel packets, and the SCSI protocol is usually implemented either in software, or through hardware assists. During the discussion of this patent, SCSI Fibre Channel protocol will be referred to as, "the FCP SCSI Protocol" so as to assist the readers in disassociating the upper level protocol for transacting SCSI operations over Fiber Channel, from the Fibre Channel Protocol proper.
While there are many different types of computer interconnects, no universal interconnect solution presently exists. Nevertheless, ATM naturally meets the requirements of LANs, MANs and WANs, and in the case of computer node interconnect for massively parallel, cluster and symmetric multi-processing, the ATM interface can be designed to provide very low latency transfers between nodes. Peripheral interconnect can also be accomplished by ATM based links. By using ATM's natural ability as a LAN, MAN and WAN together with the cited enhanced capabilities of ATM, an ATM network can be used as a universal interconnect and replace all other computer system interconnects. Thus, an ATM universal interconnect would significantly reduces interconnect cost, interconnect management, and interconnect maintenance as well as improve availability.
Accordingly, it can also be seen that there is a need for a universal computer system interconnect that includes enhanced ATM/SONET capabilities.